1. Field of the Invention
This invention relates to arbitration systems and more particularly to a look-ahead priority arbitration system and method.
2. Background of the Invention
In the prior art, there is known arbitrating systems such as in U.S. Pat. No. 4,473,880 of Budde et al, or U.S. Pat. No. 4,499,538 of Finger et al, that provide some form of arbitration system to several processors or microprocessors with a common bus. These arbitration systems with a common bus are relatively slow systems in that only an input to the bus from one unit can be applied via the bus to an output unit in a given switch cycle. Cross point switches such as switching matrix as described in U.S. Pat. No. 4,417,245 of Melas et al couple multiple inputs to multiple outputs simultaneously provided a given input does not want to conflict with another given input at the same output and assumes that some form of separate control is provided. U.S. Pat. No. 4,991,084 of Rodiger et al. discloses an arbitration round robin order switching matrix system. U.S. Pat. No. 4,313,161 of Hardin et al. discloses a shared storage for multiple processor systems utilizing a ring counter with a look-ahead feature that performs polling other processors for access to the shared storage. A look ahead bus arbitration system with an override of conditional access grants via bus cycle extensions for multi-cycle data transferred is shown in U.S. Pat. No. 4,980,854 of Donaldson et al. Other prior art disclosures of data processing systems with shared memory or bus arbitration are illustrated in the following patents: U.S. Pat. No. 4,481,572 of Ochsner, U.S. Pat. No. 4,363,094 of Kaul et al, U.S. Pat. No. 4,972,314 of Getzinger et al, U.S. Pat. No. 4,086,629 of Desyllas et al, (hierarchical data store with look-ahead action), U.S. Pat. No. 4,159,532 of Getson, Jr. et al, and U.S. Pat. No. 4,688,188 of Washington.
A computer system can include a number of resources that include processors, memories or I/O devices. It is often necessary for the command to enter data to be transferred between the different resources in a computer system. More particularly a system bus is provided for transferring data between a number of resources or nodes in a multiple node network.
The access to the bus by each of the resources must be controlled. In order to control the coupling to a number of nodes, some form of "arbitration" is performed in order to determine which node obtains access to the bus. An arbitrator determines which resource will be accessed to the bus each cycle.
Large, high band width, input queued cross bar or cross point switches are often used for processor-memory interconnection networks for shared memory multi-processor systems. In vector processing supercomputer system caches are often not effective and the majority of storage access for vector operations are directly to storage. In these cases latency of the memory sub-system, (time from the storage request to the receipted data) can significantly effect performance. It is desirable to find an arbitrator means that reduces the average request latency thereby providing system performance for supercomputing systems with this type of processor to memory interconnection for example.